Electrical components, such as capacitors, are used in electrical circuits to perform particular circuit functions. In integrated circuit (IC) technology, such components are formed using specialised IC processes in which layers of conductive materials, e.g. metal or polysilicon, are deposited on dielectric substrates, e.g. silicon dioxide, the separate conductive layers thereafter being patterned and interconnected using conductive elements, known as ‘vias’, in order to define particular component structures. The ability to interconnect the patterned conductive layers using vias, whilst maintaining electrical separation using the dielectric substrate, enables complex three-dimensional component structures to be produced with fine resolution.
Typically, a designer will aim to provide structures which are efficient in terms of their compact size, whilst attempting to maximise desirable component properties and minimise parasitic component properties.
In the case of integrated capacitors, which make use of the capacitance between separate electrical nodes, it is desirable to create structures that maximise the capacitance between the nodes. Such capacitors are commonly known as Metal-Oxide-Metal (MOM) capacitors. It is also desirable to create MOM capacitors which can be conveniently scaled and which have minimal parasitic properties, such as resistance and inductance. It will be appreciated that minimising these parasitic properties will improve the quality (Q) factor, and increase the self-resonant frequency, of the capacitor.
A known MOM capacitor structure is shown in FIGS. 1a and 1b. FIG. 1a is a plan view of the capacitor structure 2, whilst FIG. 1b is a cross-sectional view of the capacitor structure, taken along the line X—X shown in FIG. 1a. 
Referring to FIG. 1b, it will be noted that the capacitor structure 2 comprises a first metal layer, indicated ‘n’, and a second metal layer, indicated ‘n−1’, the second metal layer being located beneath the first layer. The metal layers n, n−1 are substantially coplanar and are separated by a dielectric (not shown).
Referring to FIG. 1a, it will be seen that the first metal layer n provides first and second capacitor terminals 3, 4, the terminals being arranged substantially opposite each other. The first metal layer n also provides a plurality of parallel metal fingers arranged in two interleaved groups 5, 6. For the sake of clarity, only one finger of each group 5, 6 is indicated with a reference numeral. The first group of metal fingers 5 is connected to, and extends rightwards from, the first capacitor terminal 3. However, said metal fingers do not extend as far as the second capacitor terminal 4 and so are electrically isolated therefrom. In a similar manner, the second group of metal fingers 6 is connected to, and extends leftwards from, the second capacitor terminal 4, said metal fingers being electrically isolated from the first capacitor terminal 3.
The second layer n−1 provides a similar arrangement of first and second groups of metal fingers (indicated by the reference numerals 5′, 6′ to clarify that the fingers are formed by the second layer) which are connected, respectively, to the first and second capacitor terminals 3, 4 of the first layer n. The interconnection between the first and second layers n, n−1 is made in the conventional manner using via connectors 8 which pass through the intervening dielectric layer. Referring to FIG. 1b, it will be noted that the metal fingers are also interleaved in the vertical plane such that metal fingers of the first group 5, 5′ are in respective alignment above or below metal fingers of the second group 6, 6′.
In the capacitor structure 2 represented in FIG. 1, the current flow in all fingers lies in the same direction which can result in undesirable inductive effects due to the mutual electromagnetic coupling between adjacent metal fingers. It may also be noted that additional metalisation is required using the via connectors 8 on the end of each finger in order to make the appropriate electrical connection to each capacitor terminal 3, 4.
A further known MOM capacitor structure is represented in FIGS. 2a and 2b. FIG. 2a is a plan view of this known capacitor structure 9, whilst FIG. 2b is a cross-sectional view of the capacitor structure, taken along the line Y—Y shown in FIG. 2a. 
Referring to FIG. 2b, as with the capacitor structure 2 described above, the further capacitor structure 9 comprises a first metal layer, indicated ‘n’ and a second metal layer, indicated ‘n−1’ the second metal layer being located beneath the first layer. As before, the metal layers n, n−1 are substantially coplanar and are separated by a dielectric (not shown).
Each metal layer n, n−1 provides a plurality of parallel metal fingers, the fingers of successive layers being offset by 90°. The metal fingers of the first and second layers n, n−1 are arranged to form two groups of interconnected fingers 10, 11, the two groups being electrically isolated from each other and connected to respective capacitor terminals (not shown). As FIG. 2a shows, the fingers forming each respective group 10, 11 are interconnected between the two layers n, n−1 in an alternating manner such that, in effect, a woven structure is formed. As before, interconnection between the two layers n, n−1 is achieved using via connectors 8 which are placed at any point where there are overlying fingers belonging to the same group (and so connected to the same capacitor terminal).
Since each layer n, n−1 provides parallel fingers which are connected to different capacitor terminals, some electromagnetic interaction will occur and so undesirable induction effects will again be present. Care is also necessary to ensure a low connection resistance is maintained in connecting the fingers to the appropriate capacitor terminal. The individual resistance of the via connectors 8 can be significant and so current needs to be distributed through, in effect, many parallel paths within the capacitor structure using appropriate terminal connections.